A 800 MHz-1.1 GHz 1.2 mW Delay Locked Loop with a Closed Loop Duty Cycle Corrector
نویسندگان
چکیده
منابع مشابه
A 3-8 GHz Delay-Locked Loop With Cycle Jitter Calibration
A 3–8 GHz delay-locked loop (DLL) with cycle jitter calibration is presented. To lower the operation frequency of a voltage-controlled delay line (VCDL), this DLL adopts the dividers, an edge combiner, and the multiple VCDLs. A duty cycle correction circuit is presented to maintain the output duty cycle of 50%. This DLL has been fabricated in 90-nm CMOS process. The measured peak-to-peak jitter...
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ژورنال
عنوان ژورنال: Journal of Electrical & Electronic Systems
سال: 2016
ISSN: 2332-0796
DOI: 10.4172/2332-0796.1000179